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w wm8602 2.1 channel pwm controller wolfson microelectronics plc www.wolfsonmicro.com product preview, may 2004, rev 1.5 copyright ? 2004 wolfson microelectronics plc description the wm8602 comprises a high performance stereo + sub pwm digital power amplifier controller. simply by adding appropriate power output stages a 2.1 channel power amplifier may be built. two identical full audio bandwidth channels, plus a reduced bandwidth sub channel are provided as pwm outputs. the pcm to pwm converter supports up to 2 channels of audio, in pcm input formats. the on board bass management enables the generation of a sub channel from the stereo pcm data. a graphic equaliser function is provided, plus selectable high frequency equalisation to suit different speaker types. independent volume control for each channel is provided. the wm8602 pwm controller is compatible with integrated switching output stages available from a number of vendors or alternatively may be used with a discrete output stage configuration and achieve similar levels of performance. a dynamic peak compressor with programmable attack and decay times is included, which allows headroom for tone control, bass management and extra digital gain to be provided, without clipping occurring. a synchroniser allows slaving to lrclk, thus making the wm8602 independent of source mclk frequency and jitter. the device is controlled via a 2/3 wire serial interface. the interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. the device is supplied in a 28-pin ssop package. features ? multi-channel pwm audio amplifier controller ? supports stereo input ? supports stereo or 2.1 with sub channel generation ? pwm audio performance with typical output stage ? 100db snr (a weighted @ 48khz) ? 0.01% thd @ 1watt ? 0.1% thd @ 30watt ? integrated bass management support with adjustable filter ? integrated 4-band graphic equaliser ? adjustable output stage filter compensation for different speakers ? volume control on each channel +24db to -103.5db in 0.5db steps, with volume ramping and auto-mute functions ? programmable dynamic peak compressor avoids clipping even at high volume settings ? internal pll and optional crystal oscillator, supporting audio and mpeg standards ? 2/3-wire mpu serial control interface ? master or slave clocking mode ? programmable audio data interface modes ? i 2 s, left, right justified or dsp ? 16/20/24/32 bit word lengths ? de-emphasis support for stereo ? cmos digital outputs applications ? hi-fi systems ? automotive audio ? boombox ? active speakers
wm8602 product preview w pp rev 1.5 may 2004 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 absolute maximum ratings.........................................................................5 electrical characteristics ......................................................................6 terminology .....................................................................................................7 power consumption ......................................................................................7 signal timing requirements .......................................................................8 power supply.......................................................................................................... 8 master clock timing ............................................................................................. 8 audio interface timing C master mode .......................................................... 9 device description .......................................................................................14 introduction ......................................................................................................... 14 signal path............................................................................................................. 14 digital audio interface ..................................................................................... 15 audio interface control.................................................................................. 18 master clock and audio sample rates........................................................ 19 synchroniser........................................................................................................ 22 control interface operation ........................................................................ 23 input processor .................................................................................................. 24 bass management .........................................................................................25 graphic equaliser............................................................................................... 26 digital deemphasis .............................................................................................. 28 digital volume control .................................................................................... 28 soft mute and auto-mute ................................................................................. 29 dynamic peak compressor ............................................................................... 31 interpolation filters ........................................................................................ 34 pcm to pwm converter ..................................................................................... 35 standby, output disable and reset modes ................................................ 36 external power supply clock ....................................................................... 37 register map...................................................................................................39 filter responses ................................................................................................. 40 digital de-emphasis characteristics........................................................... 41 application notes ........................................................................................42 start-up .................................................................................................................. 42 power supply connections............................................................................. 43 applications information .........................................................................44 recommended external components .......................................................... 44 recommended external components values ........................................... 44 package dimensions ....................................................................................45 important notice ..........................................................................................46 address: .................................................................................................................. 46
product preview wm8602 w pp rev 1.5 may 2004 3 pin configuration ordering information device temperature range package moisture level sensitivity peak soldering temperature wm8602seds/v -25 to + 85 c 28-pin ssop (lead free) msl1 260c wm8602seds/rv -25 to + 85 c 28-pin ssop (lead free, tape and reel) msl1 260c
wm8602 product preview w pp rev 1.5 may 2004 4 pin description pin name type description 1 dvdd supply digital positive supply 2 din digital input l/r channel data input 3 lrclk digital input/output left/right word clock 4 bclk digital io audio interface bit clock 5 opdis digital input p.d. output disable 6 mode digital input p.d. 2/3 wire control interface mode 7 sclk digital input serial interface clock 8 sdin digital input/output serial interface data 9 csb digital input serial interface load signal 10 eapdb digital output external output stage power down 11 opswp digital output pwm output positive subwoofer channel 12 bvdd supply pwm output buffer positive supply 13 agnd supply analogue negative supply 14 clkpsu digital output clock for external psu 15 bgnd supply pwm output buffer ground supply 16 bvdd supply pwm output buffer positive supply 17 oprn digital output pwm output negative right channel 18 oprp digital output pwm output positive right channel 19 bgnd supply pwm output buffer ground supply 20 opln digital output pwm output negative left channel 21 oplp digital output pwm output positive left channel 22 bvdd supply pwm output buffer positive supply 23 avdd analogue supply analogue positive supply 24 agnd analogue supply analogue negative supply 25 xop digital output crystal oscillator output connection 26 xin digital input crystal oscillator input connection (may be left unconnected in slave mode) 27 dgnd supply digital negative supply 28 mclk digital input/output master clock; 256, 384, 512 fs (fs = word clock frequency) or 27mhz notes : digital input pins have schmitt trigger input buffers. pins marked p.u. or p.d. have internal pull-up or pull down.
product preview wm8602 w pp rev 1.5 may 2004 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max analogue supply voltage (avdd) -0.3v +5v digital supply voltage (dvdd) -0.3v +5v pwm output buffer supply voltage (bvdd) -0.3v +5v voltage range inputs dgnd -0.3v dvdd +0.3v master clock frequency 10mhz 50mhz operating temperature range, t a -20 c +85 c storage temperature -65 c +150 c notes: 1. gnd power supplies (i.e. agnd, dgnd, and bgnd) must always be within 0.3v of each other. 2. vdd power supplies (i.e. avdd, dvdd, and bvdd) must always be within 0.3v of each other. recommended operating conditions parameter symbol test conditions min typ max unit analogue supply range avdd 2.7 3.6 v digital supply range dvdd 2.7 3.6 v pwm output buffer supply bvdd 2.7 3.6 v ground agnd, dgnd, bgnd 0 v
wm8602 product preview w pp rev 1.5 may 2004 6 electrical characteristics test conditions avdd, bvdd, dvdd = 2.7 to 3.3v, agnd, dgnd, bgnd = 0v, t a = -20 to +85 o c, fs = 44.1khz/48khz, mclk = 256fs unless stated. parameter symbol test conditions min typ max unit input capacitance c i 3 4 pf input leakage i leak 0.1 0.5 a oscillator input xin low level vx il 0 0.44 v input xin high level vx ih 0.77 avdd v input xin capacitance c xi 4 5 pf input xin leakage ix leak 0.10 0.11 0.13 ma output xop low vx ol 15pf load capacitors 0.1 0.4 0.5 v output xop high vx oh 15pf load capacitors 1.2 1.3 1.4 v digital logic levels (cmos levels) input low level v il 0.3 x dvdd v input high level v ih 0.7 x dvdd v pull-up/pull-down resistance 100 200 400 k ? output low v ol i ol =+1ma 0.1 x dvdd v output high v oh i ol =-1ma 0.9 x dvdd v digital logic levels (lvds levels) output differential voltage v od r t =100 ? 200 350 500 mv offset voltage v os r t =100 ? 0.95 1.25 1.4 v termination load r t 20pf load 100 ? pcm to pwm converter digital snr l, r 105 db typical snr with output stage (a-weighted) l, r 100 db typical dynamic range with output stage l, r 100 db digital thd+n at 0dbfs l, r 0.001 % typical thd+n at 30watt with output stage l, r 0.1 % typical thd+n at 1watt with typical output stage l, r 0.01 % typical imd (ccif C 19/20khz) l, r -70 dbfs typical imd (smpte C 60hz/7khz) l, r -70 dbfs pcm to pwm converter digital snr subwoofer 5 105 typical snr with output stage (a-weighted) subwoofer 5 100 typical dynamic range with output stage subwoofer 5 100 digital thd+n at 0dbfs subwoofer 5 0.001 typical thd+n at 30watt with output stage subwoofer 5 0.1 typical thd+n at 1watt with typical output stage subwoofer 5 0.01 typical imd (ccif C 19/20khz) subwoofer 5 -70 typical imd (smpte C 60hz/7khz) subwoofer 5 -70
product preview wm8602 w pp rev 1.5 may 2004 7 test conditions avdd, bvdd, dvdd = 2.7 to 3.3v, agnd, dgnd, bgnd = 0v, t a = -20 to +85 o c, fs = 44.1khz/48khz, mclk = 256fs unless stated. parameter symbol test conditions min typ max unit pwm buffer drive strength i source cmos 25 4 ma i sink 20pf load 25 4 ma fs = 44.1khz 352.8 khz pwm pulse repetition rate f pwm fs = 48khz 384 khz notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured a weighted over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz aes17 low pass filter, except where noted an a-weight filter is used. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. the xin input supports both a clock as well as a crystal input. 4. parameter guaranteed by design. 5. validated using the following filter parameter symbol test conditions min typ max unit filter stopband -3db 1.00 khz note : a third order differential rc filter has been used terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with no signal applied. 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rms values, of (noise + distortion)/signal. power consumption mode description typical supply currents [ma] total current [ma] total power [mw] i avdd i dvdd i bvdd avdd, dvdd, bvdd = 3.3v off 0 0 0 0 0 standby 0.02 0.28 0 0.30 0.99 mute 1.76 27.2 7.55 36.5 121 stereo 1.76 27.7 7.55 37.0 122 2.1 table 1 supply current consumption notes: 1. t a = +25 o c, slave mode, fs = 48khz, mclk = 27 khz, 24-bit data 2. all figures are khz 1khz input sine wave @ 0db.
wm8602 product preview w pp rev 1.5 may 2004 8 signal timing requirements power supply test conditions agnd, dgnd, bgdn = 0v, t a = +25 c parameter symbol min typ max unit power supply timing information avdd: rise time 10% to 90% avdd t ar 0.2 50 ms dvdd: rise time 10% to 90% dvdd t dr 0.2 50 ms bvdd: rise time 10% to 90% bvdd t br 0.2 50 ms table 2 power supply timing requirements master clock timing xti/mclk t mclky figure 1 master clock timing requirements test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgdn = 0v, t a = +25 c parameter symbol min typ max unit system clock timing information xti/mclk system clock cycle time t mclky 20 100 ns xti/mclk duty cycle 40:60 60:40 % xti/mclk period jitter 200 ps xti/mclk rise/fall times 10% to 90% avdd 3 ns table 3 master clock timing requirements
product preview wm8602 w pp rev 1.5 may 2004 9 audio interface timing C master mode figure 2 digital audio data timing C master mode (see control interface) test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgdn = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 10 ns din setup time to bclk rising edge t dst 10 ns din hold time from bclk rising edge t dht 10 ns table 4 audio interface timing C master mode bclk (output) lrclk (output) t dl din t dht t dst
wm8602 product preview w pp rev 1.5 may 2004 10 audio interface timing C slave mode figure 3 digital audio data timing C slave mode test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns bclk rise/fall times 5 ns lrclk set-up time to bclk rising edge t lrsu 10 ns lrclk hold time from bclk rising edge t lrh 10 ns lrclk rise/fall times 5 ns din hold time from bclk rising edge t dh 10 ns table 5 audio interface timing C slave mode note: bclk period should always be greater than or equal to mclk period.
product preview wm8602 w pp rev 1.5 may 2004 11 control interface timing C 3-wire mode csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 4 control interface timing C 3-wire serial control mode test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 60 ns sclk pulse cycle time t scy 80 ns sclk pulse width low t scl 30 ns sclk pulse width high t sch 30 ns sdin to sclk set-up time t dsu 20 ns sclk to sdin hold time t dho 20 ns csb pulse width low t csl 20 ns csb pulse width high t csh 20 ns csb rising to sclk rising t css 20 ns pulse width of spikes that will be suppressed t ps 2 8 ns table 6 control interface timing C 3-wire serial control mode
wm8602 product preview w pp rev 1.5 may 2004 12 control interface timing C 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 10 figure 5 control interface timing C 2-wire serial control mode test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 400 khz sclk low pulse-width t 1 600 ns sclk high pulse-width t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 2 8 ns table 7 control interface timing C 2-wire serial control mode
product preview wm8602 w pp rev 1.5 may 2004 13 pwm output timing opxxx t pwmh t pwml t pwmcy figure 6 pwm output timing test conditions avdd, dvdd, bvdd = 2.7 to 3.3v, agnd, dgnd, bgnd = 0v, t a = -20 to +85 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol/note min typ max unit program register input information pwm frequency t pwmcy 384 khz pwm low pulse-width t pwml 122 ns pwm high pulse-width t pwmh 122 ns cmos mode pwm rise time 1 20pf load 1.5 2.3 ns pwm fall time 1 20pf load 1.5 2.3 ns table 8 pwm interface timing note: 1. parameter guaranteed by design
wm8602 product preview w pp rev 1.5 may 2004 14 device description introduction the wm8602 is a high-performance multi-channel pulse-width modulation (pwm) digital power amplifier controller. the device accepts up to 2 channels of audio in pcm input format, and outputs 2 pwm full-bandwidth channels, plus a pwm sub-woofer channel. the outputs are suitable for directly driving integrated switching output stages available from a number of vendors. the device is also compatible with discrete mosfet output stages. in both cases, wolfson microelectronics offer reference designs for complete pwm digital power amplifiers. the wm8602 has a configurable input processor which accepts stereo channels of pcm audio and outputs stereo or 2.1 outputs. the sub channel is generated from the filtered sum of the low frequency components of the input data. the device has a bass management function, which has low-pass and high-pass filters for feeding the sub channel and main output channels. it also provides selectable boost for the lfe channel. each channel can be configured to drive either large full-range speakers or small satellite speakers with limited bass capability. a tone control function is provided, plus selectable high frequency equalisation to compensate for different loudspeaker characteristics. independent volume control is provided for all channels, with comprehensive mute features. a dynamic peak compressor with programmable attack and decay times is included, which allows headroom for tone control, bass management and extra digital gain to be provided, without clipping occurring. the device is controlled via a 2/3 wire serial interface. the interface provides access to all features including channel selection, volume controls, mute, de-emphasis and power management facilities. signal path the wm8602 receives digital input data via a 2-channel digital audio interface. the data is processed in turn by the input processor, bass management and equalisation, volume control and dynamic peak compressors, interpolation filters, and pcm-pwm converters, as shown in figure 7. the pwm signals are output via cmos drivers. figure 7 signal processing block diagram volume control / dynamic peak compressors pcm - pwm converter interpolation filters input processor bass management and equalisation cmos output 2 channel input
product preview wm8602 w pp rev 1.5 may 2004 15 parameter group delay unit fs=48khz unit l / r channel 47 samples 1.0 ms sub channel 22 samples 0.5 ms table 9 signal path group delay note: the shorter delay on the sub channel will not significantly affect audio performance. (it is equivalent to moving the subwoofer forwards by about 15cm.) digital audio interface the digital audio interface is used for inputting audio data into the wm8602. it uses five pins: ? din: l+r channel data input ? lrclk: data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk and lrclk can be outputs when the wm8602 operates as a master, or inputs when it is a slave (see master and salve mode operation, below). master and slave mode operation the wm8602 can be configured as either a master or slave mode device. as a master device the wm8602 generates bclk and lrclk and thus controls sequencing of the data transfer on the data channels. in slave mode, the wm8602 receives data and clock signals over the digital audio interface. the mode can be selected by writing to the ms bit (see table 23). master and slave modes are illustrated below. master mode slave mode figure 8 operation mode audio data formats in left justified mode, the msb is available on the first rising edge of bclk following a lrclk audio data is applied to the internal filters via the digital audio interface. 5 popular interface formats are supported: ? left justified mode ? right justified mode ? i 2 s mode ? dsp mode a ? dsp mode b all 5 formats send the msb first and support word lengths of 16, 20, 24 and 32 bits. except that 32 bit data is not supported in right justified mode. din and lrclk are sampled on the rising, or falling edge of bclk. in left justified, right justified and i 2 s modes the digital audio interface receives data on the din input. audio data for each stereo channel is time multiplexed with lrclk indicating whether the left or right channel is present. lrclk is also used as a timing reference to indicate the beginning or end of the data words. in left justified, right justified and i 2 s modes, the minimum number of bclks per daclrc period is 2 times the selected word length. lrclk must be high for a minimum of word length bclks and low for a minimum of word length bclks. any mark to space ratio on lrclk is acceptable provided the above requirements are met.
wm8602 product preview w pp rev 1.5 may 2004 16 in dsp mode a or b, all channels are time multiplexed onto din. lrclk is used as a frame sync signal to identify the msb of the first word. the minimum number of bclks per lrclk period is 8 times the selected word length. any mark to space ratio is acceptable on lrclk provided the rising edge is correctly positioned (see figure 9, figure 10 and figure 11). left justified mode in left justified mode, the msb is sampled on the first rising edge of bclk following a lrclk transition. lrclk is high during the left samples and low during the right samples. figure 9 left justified mode timing diagram right justified mode in right justified mode, the lsb is sampled on the rising edge of bclk preceding a lrclk transition. lrclk is high during the left samples and low during the right samples. figure 10 right justified mode timing diagram
product preview wm8602 w pp rev 1.5 may 2004 17 i 2 s mode in i 2 s mode, the msb is sampled on the second rising edge of bclk following a lrclk transition. lrclk is low during the left samples and high during the right samples. figure 11 i 2 s mode timing diagram dsp mode a and b in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrclk. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. figure 12 dsp mode a timing diagram figure 13 dsp mode b timing diagram
wm8602 product preview w pp rev 1.5 may 2004 18 no bclk edges are allowed between the data words. mode input format (order) supported modes stereo l, r no restrictions apply table 10 dsp mode input format audio interface control the register bits controlling audio format, word length and master/slave mode are summarised below. ms selects audio interface operation in master or slave mode. in master mode bclk and lrclk are outputs and the frequency of lrclk is set by the sample rate control bits sr[3:0]. in slave mode bclk and lrclk are inputs (refer to table 12 for sample rate control in this case). register address bit label default description 8 bclkinv 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted 7 ms 0 master / slave mode control 1 = enable master mode 0 = enable slave mode 6 lrswap 0 left/right channel swap 1 = swap left and right data in audio interface 0 = output left and right data as normal 4 lrp 0 right, left and i 2 s modes C lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity (as show in e.g. figure 12) dsp mode C a/b select 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 3:2 wl[1:0] 10 audio data word length 11 = 32 bits (see note) 10 = 24 bits 01 = 20 bits 00 = 16 bits r2 (02h) audio if format 1:0 format[1:0] 10 audio data format select 11 = dsp mode 10 = i 2 s format 01 = left justified 00 = right justified table 11 audio data format control notes: 1. right justified mode does not support 32-bit data.
product preview wm8602 w pp rev 1.5 may 2004 19 master clock and audio sample rates the wm8602 supports a wide range of master clock frequencies on the mclk pin, and can generate many commonly used audio sample rates directly from the master clock. (see table 14 for details.) register address bit label default description 0 cmast 1 master clock mode 0 = mclk input 1 = xin input 1 mpeg 1 mpeg mode 0 = see table 14 1 = mclk is 27mhz 2 medge 0 master clock active edge 0 = positive edge 1 = negative edge r0 (00h) clocking 3 clkdiv2 0 master clock divide by 2 1 = mclk is divided by 2 0 = mclk is not divided table 12 clocking and sample rate control (1) if the wm8602 is running in mpeg mode (i.e. f xin = 27mhz) the sample can be detected automatically if the srdet bit is set. in this case, the sr bits do not need programming. register address bit label default description 3:0 sr [3:0] 0000 sample rate control. refer to table 14. r1 (01h) sample rate 4 srdet 1 sample rate detect 1 = enabled (in mpeg mode only) 0 = disabled table 13 clocking and sample rate control (2) the clocking of the wm8602 is controlled using the clkdiv2 and sr control bits. setting the clkdiv2 bit divides mclk by two internally. each value of sr[3:0] selects one combination of mclk division ratios and hence one combination of sample rates (see next page). since all sample rates are generated by dividing mclk, their accuracy depends on the accuracy of mclk. if mclk changes the sample rates change proportionally.
wm8602 product preview w pp rev 1.5 may 2004 20 mclk / xin audio sample rate sr [3:0] (mpeg = 0) clkdiv2=0 clkdiv2=1 [mhz] [mhz] [khz] 32 (mclk/384) 0001 12.288 24.576 48 (mclk/256) 0000 96 (mclk/256) 0011 24.576 49.152 192 (mclk/128) 0010 11.2896 22.5792 44.1 (mclk/256) 0100 88.2 (mclk/256) 0111 22.5792 45.1584 176.4 (mclk/128) 0110 32 (mclk/512) 1001 18.432 36.864 48 (mclk/384) 1000 96 (mclk/384) 1011 36.864 not supported 192 (mclk/192) 1010 16.9344 33.8688 44.1 (mclk/384) 1100 88.2 (mclk/384) 1111 33.8688 not supported 176.4 (mclk/192) 1110 (mpeg = 1) 32 0001 44.1 0100 48 0000 88.2 0111 96 0011 176.4 0110 27.000 not supported 192 0010 table 14 master clock and sample rates the following figure 14, figure 15, figure 16 and figure 17 illustrate the different clocking and audio if modes. figure 14 clock and audio if: clock master / audio if slave (default)
product preview wm8602 w pp rev 1.5 may 2004 21 figure 15 clock and audio if: clock master / audio if master figure 16 clock and audio if: clock slave / audio if slave figure 17 clock and audio if: clock slave / audio if master
wm8602 product preview w pp rev 1.5 may 2004 22 synchroniser the wm8602 contains a synchroniser circuit to support the synchronisation of an external lrclk to the local lrclk. this mode is only supported in mpeg mode. the specification of the synchroniser circuit is: test conditions avdd, dvdd, bvdd = 3.3v, agnd, dgnd, bgnd = 0v, t a = +25 o c, f xin = 27mhz, slave mode, fs = 48khz, 24-bit data, unless otherwise stated. parameter symbol min typ max unit lock time t lock <1 2 s lrclk frequency offset f offlrclk 1000 10000 ppm f s 0.2 ppm/s lrclk drift in lock drift lrclk 6 hz table 15 synchroniser specification register address bit label default description 0 syncen 1 synchroniser enable 0: disable 1: enable (in mpeg mode only) 2:1 gmin[1:0] 10 minimum synchroniser gain 00: minimum gain = 2 0 01: minimum gain = 2 1 10: minimum gain = 2 2 11: minimum gain = 2 3 4:3 gmax[1:0] 10 maximum synchroniser gain 00: maximum gain = 2 8 01: maximum gain = 2 10 10: maximum gain = 2 12 11: maximum gain = 2 14 r32 (20h) synchroniser (1) 5 hold 0 hold synchroniser (and sr detect) 1 : synchroniser in hold mode table 16 synchroniser (1) register address bit label default description r33 (21h) synchroniser (2) 2:0 synto[2:0] 100 synchroniser gain time-out 000: 0.2 ms 001: 0.5 ms 010: 1 ms 011: 2 ms 100: 5 ms (default) 101: 10 ms 110: 20 ms 111: 50 ms table 17 synchroniser (2) the next table illustrates recommendation for the synchroniser loop gain g (see also table 16) and time-out time (table 17) with respect to the lrclk frequency and the resulting synchroniser lock time.
product preview wm8602 w pp rev 1.5 may 2004 23 g f offlrclk [ppm] max min gain time-out [ms] 100 2 8 2 0 ~1 1000 2 10 2 0 ~4 10000 2 10 2 0 ~20 table 18 synchroniser setup and locking note: the synchroniser requires a continuously running lrclk. if that is not the case the hold signal has to be applied to avoid the synchronizer drifting. control interface operation selection of control mode the wm8602 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin selects the interface format. an internal pull-down resistor configures the control interface to a default 2 wire format. mode interface format low 2 wire (default) high 3 wire table 19 control interface mode selection the wm8606 control interface operates as a slave device only. 3-wire (spi compatible) serial control mode the wm8602 is controlled using a 3-wire serial interface. sdin is used for the program data, sclk is used to clock in the program data and csb is use to latch in the program data. the 3-wire interface protocol is shown in figure 13. csb sclk sdin b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 18 3-wire serial interface the bits b[15:9] are control address bits and the bits b[8:0] are control data bits 2-wire serial control mode the wm8602 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8602). the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8602 and the r/w bit is 0, indicating a write, then the wm8602 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is 1, the wm8602 returns to the idle condition and wait for a new start condition and valid address.
wm8602 product preview w pp rev 1.5 may 2004 24 once the wm8602 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8602 register address plus the first bit of register data). the wm8602 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8602 acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8602 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 18 2-wire serial control interface the wm8602 has two possible device addresses, which can be selected using the csb pin. csb state device address low 0011010 high 0011011 table 20 2-wire mpu interface address selection input processor the wm8602 supports the production of stereo or 2.1 outputs from stereo inputs according to table 21. output configurations config fl out fr out sub out stereo ? ? 2.1 ? ? ? table 21 output configuration
product preview wm8602 w pp rev 1.5 may 2004 25 register address bit label default description r3 (03h) input/output configuration 3 opcfg[1:0] 1 output configuration 0 = stereo 1 = 2.1 table 22 input and output configuration register the wm8602 also supports stereo input C stereo output via the bass management filtering options, as discussed in bass management (page 25). in this case, the output configuration is set to 2.1. where there are a different number of input and output channels, the data is processed as follows. refer to the section on bass management (page 25) for details on how the sub-channel is created. stereo input C stereo output the left and right inputs are passed to the left and right outputs. all other channels are muted. stereo input C 2.1 output the left and right inputs are passed to the left and right outputs. the low-frequency contents of the left and right inputs, may be optionally mixed and passed to the sub output. bass management the bass-management function filters and combines the input signals to produce a low-pass filtered output for the sub-woofer channel and high-pass filtered outputs for the remaining channels. the filters have selectable cut-off frequencies to match different types of sub-woofer and satellite speakers. the filters are designed so that the cut-off frequencies for the high-pass and low-pass filters remain constant irrespective of the sampling frequency used. 1 st order filters are used for the low-pass and high-pass filters. figure 19 bass management the high-pass filters pairs can be bypassed to allow full-range speakers to be used on the main output pair. the bass-management also provides a selectable lfe boost of 10db via the lfeboost control bit. additional gain-adjust is provided after this block (refer to digital volume control, page 28).
wm8602 product preview w pp rev 1.5 may 2004 26 register address bit label default description 1:0 lphpco[1:0] 01 low-/high-pass cutoff frequency (-3db) 00 = 75hz 01 = 100hz 10 = 133hz 11 = 178hz r13 (0dh) bass management filter 2 lfeboost 0 lfe boost enable 0 = boost disabled 1 = 10db boost enabled table 23 bass management filter register address bit label default description r14 (0eh) bass management 0 hpenf 1 left/right high-pass filter 0 = high-pass filter bypassed 1 = high-pass filter enabled filter bypass 3 lpenf 1 left/right low-pass filter enable 0 = low-pass filter output disabled 1 = low-pass filter output enabled table 24 bass management filter bypass graphic equaliser the wm8602 has a 4-band graphic equaliser on the main channels. the three upper bands are controlled via registers (see table 25, table 26, table 27 and table 28). the lowest band is controlled via the subwoofer volume control (see vols in table 31). the function has selectable cut- off frequencies which are independent of sample rate. the boost/cut for the upper three bands is controllable in 1.5db steps from -6db to +9db via the eqb control bits. register address bit label default description r15 (0fh) eq band 1 gain control 3:0 eq1gf [3:0] 1111 (disabled) band 1 left/right gain 0000 or 0001 = +9db 0010 = +7.5db (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 25 eq band 1 gain control register address bit label default description r16 (10h) eq band 2 gain control 3:0 eq2gf [3:0] 1111 (disabled) band 2 left/right gain 0000 or 0001 = +9db 0010 = +7.5db (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 26 eq band 2 gain control
product preview wm8602 w pp rev 1.5 may 2004 27 register address bit label default description r17 (11h) eq band 3 gain control 3:0 eq3gf [3:0] 1111 (disabled) band 3 left/right gain 0000 or 0001 = +9db 0010 = +7.5db (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 27 eq band 3 gain control register address bit label default description 0 eq1cf 1 band 1 left/right centre-frequency 0 = high cutoff (500hz) 1 = low cutoff (250hz) 2 eq2cf 1 band 2 left/right centre-frequency 0 = high cutoff (2khz) 1 = low cutoff (1khz) r18 (12h) eq centre- frequency control 4 eq3cf 1 band 3 left/right cutoff frequency 0 = high cutoff (8khz) 1 = low cutoff (4khz) table 28 eq frequency control band 0 is controlled via the sub-woofer volume control register r11 as described in table 31. the functionality to add/subtract the boost/cut setting to the sub-woofer volume must be written into the software controller for the chip. the band 0 cutoff frequency can be changed using the corner frequency of the low-pass/high-pass filters as described in table 23. digital loudspeaker equaliser a loudspeaker equaliser is provided to compensate for high-frequency variations that can occur when loudspeakers of different impedances are used with different output filters in typical output stages. the equaliser has selectable cut-off frequencies which are independent of sample rate. the gain at 20khz is controllable in 0.5db steps from -1.5db to +2db via the lseq control bit. the settings are applied to left and right channels simultaneously. register address bit label default description 0 lsco 0 lseq filter characteristic 0 = high cutoff (15khz) 1 = low cutoff (10khz) r19 (13h) loudspeaker equaliser 3:1 lseq [2:0] 100 (disabled) high frequency equalisation 000 = +2db 001 = +1.5db 010 = +1db 011 = +0.5db 100 = disable 101 = -0.5db 110 = -1db 111 = -1.5db table 29 loudspeaker equaliser
wm8602 product preview w pp rev 1.5 may 2004 28 digital deemphasis the digital de-emphasis is used to equalize pre-emphasised digital cd recordings. de-emphasis filtering is available on the left and right channels only, for sample rates of 32khz, 44.1khz and 48khz. the settings are applied to the two channels simultaneously. register address bit label default description r20 (14h) de-emphasis 0 deemp 0 de-emphasis control 0 = no de-emphasis 1 = de-emphasis enabled table 30 de-emphasis refer to figure 30, figure 31, figure 32, figure 33, figure 34 and figure 35 for details of the de- emphasis modes at different sample rates. note: using the de-emphasis filters for other sample rates as defined above will result in a frequency response error as shown in figure 31, figure 33 and figure 35. digital volume control the volume control allows the gain of each channel to be independently adjusted in 0.5db steps from -103.5db to +24db. when the dynamic peak compressor (see below) is enabled, gains of greater than 0db can be applied without digital clipping occurring. the volume control has a digital zero-cross circuit which minimises clicks during changing the volume. an update control bit is provided which allows the volume setting on each channel to be first stored in an intermediate latch, then afterwards applied simultaneously to all channels. if update=0, the volume value will be written to the pre-latch but not applied to the relevant channel. if update=1, all pre-latched values will be applied from the next input sample. the value of update itself is not latched. to prevent audible clicks , the volume control incl udes a ramp function which automatically ramps the volume in small steps between register updates. the ramp rate is 256db/s 5%. register address bit label default description 7:0 voll[7:0] 10110001 (-15db) left volume in 0.5db steps. refer to table 14 r4 (04h) left volume 8 update 0 volume update 0 = store lvol in intermediate latch (no gain change) 1 = store and update all channel gains 7:0 volr [7:0] 10110001 (-15db) right volume in 0.5db steps. refer to table 14 r5 (05h) right volume 8 update 0 volume update 0 = store rvol in intermediate latch (no gain change) 1 = store and update all channel gains 7:0 vols [7:0] 10110001 (-15db) sub volume in 0.5db steps. refer to table 14 r10 (0ah) subwoofer volume 8 update 0 update 0 = store svol in intermediate latch (no gain change) 1 = store and update all channel gains table 31 volume control
product preview wm8602 w pp rev 1.5 may 2004 29 volxx[7:0] volume level 00(hex) - db (mute) 01(hex) -103db : : : : cf(hex) 0db : : : : fe(hex) +23.5db ff(hex) +24db table 32 volume control levels dual volume control setting the dvc register bit causes the volume settings to be applied in pairs. for example, the dvcf causes the left channel volume settings to be applied to both the left and right channels from the next audio input sample. no update to the vol registers is required for dvc to take effect. register address bit label default description r11 (0bh) dual volume control 0 dvcf 0 dual volume control C left/right channels: 0 : use volfr setting for right channel 1: apply volfl setting to right channel table 33 dual volume control soft mute and auto-mute the wm8602 has a soft mute function set by the smute control bit. figure 20 shows the application and release of smute while a full amplitude sinusoid is being played at 48khz sampling rate. when smute (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the dc level of the last input sample. the output will decay towards zero with a time constant of approximately 64 input samples. when smute is turned off, the output will restart almost immediately from the current input sample, thus possibly causing a pop sound. this function is disabled by default.
wm8602 product preview w pp rev 1.5 may 2004 30 figure 20 application and release of soft mute an auto-mute function is provided which automatically mutes the output stage when a digital silence period is detected. digital silence is defined as a consecutive period of 1024 zero input samples at the output of the volume control. auto-mute will be removed as soon as the volume control output becomes non-zero. (please note that on the sub channel the noise level is greatly reduced, rather than complete digital silence.) to achieve digital silence, you can do one of the following: ? turn on auto-mute and set the volume control to zero. ? turn on auto-mute and input zero data on the serial data input pins with the bass management filters disabled. (page 25) ? turn on auto-mute and soft mute. the auto-mute operates independently for left/right and subwoofer channels and can be enabled or disabled separately. the mute features maximize the snr of the pwm amplifier system. soft-mute will only maximize the snr for left/right or subwoofer channels if enabled. register address bit label default description 0 smute 0 digital soft mute 0 = disable (signal active) 1= enable 1 amutef 1 left/right auto-mute 0 = disable 1 = enable r12 (0ch) mute 4 amutesb 1 subwoofer auto-mute 0 = disable 1 = enable table 34 mute -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s)
product preview wm8602 w pp rev 1.5 may 2004 31 dynamic peak compressor the wm8602 includes a dynamic peak compressor for each channel, which prevents the occurrence of digital clipping when gains in excess of 0db are applied. the compressor automatically adjusts the signal amplitude to allow headroom for the lfe boost, sub-woofer mixing, tone controls, loudspeaker equalisation and digital volume control. the compressor has a programmable limit threshold, programmable attack and decay time-constants, a frequency-dependent decay mode, and built-in zero-cross detect. the compressor can be configured either to operate independently on all channels (dual mono), or on linked channel-pairs (stereo). compressor threshold the compressor has a digital peak detector which tracks the maximum input signal level at the output of the volume control. with reference to figure 21, if this signal is below the threshold set by control bit thresh, the compressor operates transparently with no change to the signal level. however, if peak signal rises above the threshold, the gain through the compressor is modified so that the upper part of the curve is followed. this ensures that the output signal does not exceed 0db. attack and decay times the attack time-constant atk controls how fast the gain is reduced when the signal goes above the threshold. it is defined as the time taken for the gain to reduce by 6db. normally a short attack time- constant is used to prevent the signal clipping when a high-amplitude transient occurs. the decay time-constant dcy controls how fast the gain is increased when the signal begins to fall again. it is defined as the time taken for the gain to increase by 6db. normally, the decay time- constant is much longer than the attack time-constant, to prevent the input signal from entering repeated limiting cycles. the frequency-dependent decay feature automatically detects the input frequency and sets the decay time to decay slower for low frequency signals. this reduces low-frequency signal distortion by preserving the waveform of each input cycle, whilst allowing the compressor to respond quickly to high frequency transients. this feature is enabled via the fdep control bit. 0db output level (db) peak input level [db] thresh [db] 0 -6 -12 +6 +12 -18 -24 -30 -36 -12 -18 -24 -30 -36 0db -6db -12db +6db +12db typical volume control setting figure 21 dynamic peak compressor characteristics
wm8602 product preview w pp rev 1.5 may 2004 32 register address bit label default description r21 (15h) left/right channels dynamic peak compressor 0 plenf 1 left/right channel compressor enable 0 = disable 1 = enable table 35 left/right channel dynamic peak compressor (1) register address bit label default description 2:0 atk[2:0] 010 left/right channel attack rate 000 = 170s 001 = 330s 010 = 670s 011 = 1.33ms 100 = 2.67ms 101 = 5.33ms 110 = 10.7ms 111 = 20.1ms 5:3 dcy[2:0] 011 left/right channel decay rate 000 = 340ms 001 = 680ms 010 = 1.36s 011 = 2.73s 100 = 5,46s 101, 110, 111 = 10.9s 7:6 thresh[1:0] 11 left/right channel compressor thresholds 00 = -12db 01 = -9db 10 = -6db 11 = -3db r22 (16h) left/right channels dynamic peak compressor 8 fdep 0 frequency-dependent decay 0 = disable 1 = enable table 36 left/right channel dynamic peak compressor (2) register address bit label default description r23 (17h) sub channel dynamic peak compressor 0 plensub 1 sub channel compressor enable 0 = disable 1 = enable table 37 subwoofer channel dynamic peak compressor (1)
product preview wm8602 w pp rev 1.5 may 2004 33 register address bit label default description 2:0 atk[2:0] 010 sub channel attack rate 000 = 170s 001 = 330s 010 = 670s 011 = 1.33ms 100 = 2.67ms 101 = 5.33ms 110 = 10.7ms 111 = 20.1ms 5:3 dcy[2:0] 011 sub channel decay rate 000 = 340ms 001 = 680ms 010 = 1.36s 011 = 2.73s 100 = 5,46s 101, 110, 111 = 10.9s 7:6 thresh[1:0] 11 sub channel compressor thresholds 00 = -12db 01 = -9db 10 = -6db 11 = -3db r24 (18h) sub channel dynamic peak compressor 8 fdep 0 frequency-dependent decay 0 = disable 1 = enable table 38 subwoofer channel dynamic peak compressor (2) zero-cross detect the dynamic peak compressor has a zero-cross detect which minimises clicks during gain changes. the zero-cross detect can be enabled/disabled for left/right or subwoofer channels. the zero-cross has a timeout feature which ensures that the volume will change even if the input has a large dc offset. once a new gain has been requested from the dynamic peak compressor, the zero-cross detector will wait for a zero-cross for 25 to 50 ms before applying the gain change. register address bit label default description 0 zcf 1 zero-cross enable C left/right channels: 0 : disable zero-cross 1: enable zero-cross 3 zcsub 1 zero-cross enable C sub channel: 0 : disable zero-cross 1: enable zero-cross r25 (19h) volume control zero- cross 4 zct 1 zero cross timeout enable: 0 : disable zero-cross timeout 1: enable zero-cross timeout table 39 volume control zero-cross
wm8602 product preview w pp rev 1.5 may 2004 34 interpolation filters the wm8602 uses two types of interpolation filters, selected according to sampling frequency, as shown in table 39. sampling frequency filter type interpolation main channels main channels sub 32khz 0 12x 6x 44.1khz 0 8x 4x 48khz 0 8x 4x 88.2khz 0 4x 2x 96khz 0 4x 2x 176.4khz 1 2x 1x 192khz 1 2x 1x table 40 interpolation filter types filter type 0 parameter symbol test conditions min typ max unit filter passband 0.05 db 0.454 f s stopband -3db 0.484 f s passband ripple 0.05 db stopband attenuation f > 0.546fs -60 db group delay 23 samples table 41 digital filter 0 characteristics filter type 1 parameter symbol test conditions min typ max unit filter passband 0.242 f s stopband 0.723 f s passband ripple 0.05 db stopband attenuation -60 db group delay 6 samples table 42 digital filter 1 characteristics the subwoofer filter characteristic is defined in table filter type subwoofer parameter symbol test conditions -0.1db -3db unit sample rate 32k 2.0 10.7 khz 44k1 2.7 14.5 khz 48k 3.0 15.8 khz 88k2 6.1 32.1 khz 96k 6.8 34.9 khz 176k * * khz 192k * * khz table 43 subwoofer filter characteristic note: * indicates no interpolation filters
product preview wm8602 w pp rev 1.5 may 2004 35 pcm to pwm converter the pcm to pwm converter converters the pulse-code modulated (pcm) signal into a highly linear pulse-width modulated (pwm) signal. table 44 defines the pulse repetition frequency, (prf), output clock rate (obclk) and minimum pulse width for each supported sampling frequency. t pwm p t pwm p t pwmm t pwmm t obclk figure 22 pcm to pwm converter the prf frequency (t pwmp ) of the sub-woofer channel is half of the frequency defined in table 44 in order to reduce power dissipation in the output stage. prf (1/t pwmp ) main channel sub output bitclock frequency (1/t obclk ) minimum pulse width (t pwmm ) sampling frequency [khz] [khz] [mhz] [ns] 32khz 384 192 98.304 122 44.1khz 352.8 176.4 90.3168 133 48khz 384 192 98.304 122 88.2khz 352.8 176.4 90.3168 133 96khz 384 192 98.304 122 176.4khz 352.8 176.4 90.3168 133 192khz 384 192 98.304 122 table 44 output bitclock frequency notes: 1. the correct output bitclock frequency (t obclk ) is generated by the built-in pll of the wm8602 device. the incoming clock must meet the jitter specification defined in table 3. output phase the phase control word determines whether the output of each channel is non-inverted or inverted. register address bit label default description bit channel phase 0 l 1 = invert 1 r 1 = invert r26 (1ah) output phase 6:0 ph[6:0] 0000000 6 sub 1 = invert table 45 phase
wm8602 product preview w pp rev 1.5 may 2004 36 pwm output configuration the pwm output format can be defined with the pwmcfg setting defined in table 46. register address bit label default description 2:1 pwmcfg [1:0] 00 pwm output state when output disabled or in standby mode: 01 = all pwm outputs high 00 = all pwm outputs low 10, 11 = high impedance 3 pwmph 1 pwm output phase 0 = pwm outputs in phase 1 = pwm outputs phase shifted to each other r27 (1bh) pwm output configuration 7 pwmclk 0 pwm output clock 0 = disabled 1 = enabled table 46 pwm output configuration output configuration if required the wm8602 device can be disabled in a system by setting the tri bit as defined in table 47. setting the tri bit will set all output pins of the device to high impedance. register address bit label default description r28 (1ch) output configuration 0 tri 0 output pins mode 0 = normal 1 = high impedance table 47 output configuration standby, output disable and reset modes standby setting the stdby register bit selects a low power mode, and immediately configures the output to produce an output defined in table 46 (pwmcfg). all trace of the previous input samples is removed, but all control register settings are preserved. output disable (opdis) pin and register (opdisr) the opdis pin is provided to immediately shutdown the outputs, primarily for their protection. this is useful for short-circuit or thermal protection. the opdis pin can be configured in 2 modes: ? synchronous ? latched in synchronous mode if opdis is high for longer than 100ns the outputs will be disabled. they will be enabled again at the end of a processing frame when opdis goes low for longer than 100ns. in latched mode if opdis is high for longer than 100ns, the outputs will be disabled and will remain off until opdis is reset via the control interface and the end of a processing frame is reached (table 49). the output disable register (opdisr) also allows the pwm outputs to be disabled via a register write. if opdisr is set the pwm outputs will be disabled at the end of the next processing frame and enabled if opdisr is reset at the end of the next processing frame.
product preview wm8602 w pp rev 1.5 may 2004 37 register address bit label default description 0 stdby 1 standby select: 0 : normal mode 1: standby mode 1 opdisr 0 output disable register 0: normal mode 1: pwm output disabled r29 (1dh) power down 2 mena 1 opdis mode 0 : synchronous 1: latched, reset via control i/f table 48 power down external application power-down (eapdb) pin the state of the output pin eapdb shows whether the device is disabled (i.e. opdis i nput pin active or stdby register set). eapdb state description 1 the device is operating correctly external application power down 0 (default) the outputs are disabled or the wm8602 device is in standby (default) mode table 49 eapdb pin reset the wm8602 device can be reset writing to the reset register as defined in table 50. register address bit label default description 0 rlena 0 writing 1 to bit 0 of the register will reset opdis r30 (1eh) reset all reset 0 writing all 1s to the register will reset the device and register settings table 50 reset note: reset or rlena will be applied at the end o f the register write and released at the beginning of the next register write. i.e. to reset the opdis register write 1 to bit 0 of the reset register and them write 0 to bit 0. external power supply clock the wm8602 device can generate a clock signal for an external psu (power supply unit) which is available at the clkpsu pin. clkpsu t pclkpsu t hclkpsu figure 23 external power supply clock
wm8602 product preview w pp rev 1.5 may 2004 38 register address bit label default description 0 enpsu 0 clkpsu enable 1: enabled 2:1 clkpsu[1:0] 00 clkpsu frequency 00: clkpsu = f prf 01: clkpsu = f prf /2 10: clkpsu = f prf /4 11: clkpsu = f prf /6 r31 (1fh) psu 4:3 dcypsu[1:0] 00 clkpsu duty cycle 00: t hclkpsu /t pclkpsu = 0.5 (50%) 01: t hclkpsu /t pclkpsu = 0.125 (12.5%) 10: t hclkpsu /t pclkpsu = 0.0625 (6.25%) 11: t hclkpsu /t pclkpsu = 0.03125 (3.125%) table 51 psu clock note: see table 44 for specification of f prf .
product preview wm8602 w pp rev 1.5 may 2004 39 register map the complete register map is shown below. the detailed description can be found in the relevant text of the device description. there are 30 registers with 9 bits per register. these can be controlled using the control interface. register address remarks bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default page ref r0 (00h) 00_0000 clocking 0 0 0 0 0 clkdiv2 medge mpeg cmast 0_0000_0011 19 r1 (01h) 00_0001 sample rate 0 0 0 0 srdet sr 0_0001_0000 19 r2 (02h) 00_0010 audio if format bclkinv ms lrswap 0 lrp wl format 0_0000_1010 18 r3 (03h) 00_0011 input/output configuration 0 0 0 0 1 opcfg 0 0 1 0_0001_1001 25 r4 (04h) 00_0100 left volume update volfl (left) volume 0_1011_0001 28 r5 (05h) 00_0101 right volume update volfr (right) volume 0_1011_0001 28 r10 (0ah) 00_1010 subwoofer volume update vols (subwoofer) volume 0_1011_0001 28 r11 (0bh) 00_1011 dual volume control 0 0 0 0 0 0 0 0 dvcf 0_0000_0000 29 r12 (0ch) 00_1100 mute 0 0 0 0 amutesb 1 1 amutef smute 0_0001_1110 30 r13 (0dh) 00_1101 bass (1) 0 0 0 0 0 0 lfeboost lphpco 0_0000_0001 26 r14 (0eh) 00_1110 bass (2) 0 0 0 1 1 lpenf 1 1 hpenf 0_0011_1111 26 r15 (0fh) 00_1111 eq band 1 gain control 0 1 1 1 1 eq1gf 0_1111_1111 26 r16 (10h) 01_0000 eq band 2 gain control 0 1 1 1 1 eq2gf 0_1111_1111 26 r17 (11h) 01_0001 eq band 3 gain control 0 1 1 1 1 eq3gf 0_1111_1111 27 r18 (12h) 01_0010 eq frequency control 0 0 0 1 eq3cf 1 eq2cf 1 eq1cf 0_0011_1111 27 r19(13h) 01_0011 speaker equaliser 0 0 0 0 0 lseq lsco 0_0000_1000 27 r20 (14h) 01_0100 deemphasis 0 0 0 0 0 0 0 0 deemph 0_0000_0000 28 r21 (15h) 01_0101 peak compressor f (1) 0 0 0 0 0 0 0 0 plenf 0_0000_0001 32 r22 (16h) 01_0110 peak compressor f ( 2 ) f d ep thresh dcy atk 0_1101_1010 32 r23 (17h) 01_0111 peak compressor sub (1) 0 0 0 0 0 0 0 0 plensub 0_0000_0001 32 r24 (18h) 01_1000 peak compressor sub (2) fdep thresh dcy atk 0_1101_1010 33 r25 (19h) 01_1001 zero cross 0 0 0 0 zct zcsub 1 1 zcf 0_0001_1111 33 r26 (1ah) 01_1010 output phase 0 0 ph 0_0000_0000 35 r27 (1bh) 01_1011 pwm output config 0 pwmclk 0 0 0 pwmph pwmcfg 0 0_0000_1000 36 r28 (1ch) 01_1100 output config 0 0 0 0 0 0 0 0 tri 0_0000_0000 36 r29 (1dh) 01_1101 power down 0 0 0 0 0 0 mena opdisr stdby 0_0000_0101 37 r30 (1eh) 01_1110 reset 0 0 0 0 0 0 0 0 rlena 0_0000_0000 37 r31 (1fh) 01_1111 psu 0 0 0 0 dcypsu clkpsu enpsu 0_0000_0000 38 r32 (20h) 10_0000 synchroniser (1) 0 0 0 hold gmax gmin syncen 0_0001_0101 22 r33 (21h) 10_0001 synchroniser (2) 0 0 0 0 0 0 synto 0_0000_0100 22 table 52 register map description
wm8602 product preview w pp rev 1.5 may 2004 40 digital filter characteristics filter responses -80 -70 -60 -50 -40 -30 -20 -10 0 10 00.511.522.53 frequency (fs) response (db) figure 24 digital filter frequency response C 32khz -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0 0.10.20.30.40.5 frequency (fs) response (db) figure 25 digital filter ripple C32khz -80 -70 -60 -50 -40 -30 -20 -10 0 10 00.511.522.53 frequency (fs) response (db) figure 26 digital filter frequency response C 44.1, 48 and 96khz -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0 0.10.20.30.40.5 frequency (fs) response (db) figure 27 digital filter ripple C44.1, 48 and 96khz -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 0.2 0.4 0.6 0.8 1 frequency (fs) response (db) figure 28 digital filter frequency response C 176.4khz and 192khz -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0 0.10.20.30.40.5 frequency (fs) response (db) figure 29 digital filter ripple C 176.4khz and 192khz
product preview wm8602 w pp rev 1.5 may 2004 41 digital de-emphasis characteristics -12 -10 -8 -6 -4 -2 0 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) figure 30 de-emphasis frequency response (32khz) -6 -5 -4 -3 -2 -1 0 1 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) figure 31 de-emphasis error (32khz) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 frequency (hz) response (db) figure 32 de-emphasis frequency response (44.1khz) -6 -5 -4 -3 -2 -1 0 1 0 5000 10000 15000 20000 frequency (hz) response (db) figure 33 de-emphasis error (44.1khz) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 frequency (hz) response (db) figure 34 de-emphasis frequency response (48khz) -6 -5 -4 -3 -2 -1 0 1 0 5000 10000 15000 20000 frequency (hz) response (db) figure 35 de-emphasis error (48khz)
wm8602 product preview w pp rev 1.5 may 2004 42 application notes start-up the wm8602 per default is switched off and the pwm output pins are static high, to protect any external circuit. when the device has been properly initialized and the output configuration has been defined then the device can safely be switched on. a typical start-up sequence is show in figure 36. figure 36 wm8602 start-up
product preview wm8602 w pp rev 1.5 may 2004 43 power supply connections the wm8602 has 3 individual power supplies. figure 37 shows how these power supplies are connected and used on the chip and package. figure 37 wm8602 power supply connections
wm8602 product preview w pp rev 1.5 may 2004 44 applications information recommended external components figure 38 wm8602 external component diagram recommended external components values component reference suggested value description y1 24.576 / 27.000mhz crystal (15pf load, 500 w) c1, c2 22pf capacitor np0 0603 c3 4.7f capacitor y5v 0805 c4-c7 0.1f capacitor x7r 0603 table 53 external components description
product preview wm8602 w pp rev 1.5 may 2004 45 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ah. refer to this specification for further details. dm007.d ds: 28 pin ssop (10.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- 0.25 a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 a a2 a1 14 1 15 28 e1 e c l gauge plane 0.25 e b d seating plane -c- 0.10 c ref: jedec.95, mo-150 e 1 l 1 0.125 ref 0.65 bsc l 1 0 o 4 o 8 o
wm8602 product preview w pp rev 1.5 may 2004 46 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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